Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems

Chris S. Edrington; Michael Steurer; James Langston; Touria El-Mezyani; Karl Schoder

doi:10.1109/JPROC.2015.2460676

Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems

Chris S. Edrington, Michael Steurer, James Langston, Touria El-Mezyani, Karl Schoder

Florida State University

Research output: Contribution to journal › Article › peer-review

Original language	English
Article number	7289345
Pages (from-to)	2401-2409
Number of pages	9
Journal	Proceedings of the IEEE
Volume	103
Issue number	12
DOIs	https://doi.org/10.1109/JPROC.2015.2460676
State	Published - Dec 1 2015
Externally published	Yes

ASJC Scopus Subject Areas

General Computer Science
Electrical and Electronic Engineering

Keywords

Controller hardware in the loop (CHIL)
device under test (DUT)
field-programmable gate array (FPGA)
hardware under test (HUT)
modeling and simulation
power hardware in the loop (PHIL)
rest of system (ROS)

Access to Document

10.1109/JPROC.2015.2460676

Cite this

@article{dec04baa5b1f4e798772e8c957774422,

title = "Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems",

keywords = "Controller hardware in the loop (CHIL), device under test (DUT), field-programmable gate array (FPGA), hardware under test (HUT), modeling and simulation, power hardware in the loop (PHIL), rest of system (ROS)",

author = "Edrington, {Chris S.} and Michael Steurer and James Langston and Touria El-Mezyani and Karl Schoder",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.",

year = "2015",

month = dec,

day = "1",

doi = "10.1109/JPROC.2015.2460676",

language = "English",

volume = "103",

pages = "2401--2409",

number = "12",

}

TY - JOUR

T1 - Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems

AU - Edrington, Chris S.

AU - Steurer, Michael

AU - Langston, James

AU - El-Mezyani, Touria

AU - Schoder, Karl

PY - 2015/12/1

Y1 - 2015/12/1

KW - Controller hardware in the loop (CHIL)

KW - device under test (DUT)

KW - field-programmable gate array (FPGA)

KW - hardware under test (HUT)

KW - modeling and simulation

KW - power hardware in the loop (PHIL)

KW - rest of system (ROS)

UR - http://www.scopus.com/inward/record.url?scp=84959505007&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84959505007&partnerID=8YFLogxK

U2 - 10.1109/JPROC.2015.2460676

DO - 10.1109/JPROC.2015.2460676

M3 - Article

AN - SCOPUS:84959505007

SN - 0018-9219

VL - 103

SP - 2401

EP - 2409

JO - Proceedings of the IEEE

JF - Proceedings of the IEEE

IS - 12

M1 - 7289345

ER -

Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems

ASJC Scopus Subject Areas

Keywords

Access to Document

Other files and links

Cite this