TY - JOUR
T1 - Role of Power Hardware in the Loop in Modeling and Simulation for Experimentation in Power and Energy Systems
AU - Edrington, Chris S.
AU - Steurer, Michael
AU - Langston, James
AU - El-Mezyani, Touria
AU - Schoder, Karl
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/12/1
Y1 - 2015/12/1
KW - Controller hardware in the loop (CHIL)
KW - device under test (DUT)
KW - field-programmable gate array (FPGA)
KW - hardware under test (HUT)
KW - modeling and simulation
KW - power hardware in the loop (PHIL)
KW - rest of system (ROS)
UR - https://www.scopus.com/pages/publications/84959505007
UR - https://www.scopus.com/pages/publications/84959505007#tab=citedBy
U2 - 10.1109/JPROC.2015.2460676
DO - 10.1109/JPROC.2015.2460676
M3 - Article
AN - SCOPUS:84959505007
SN - 0018-9219
VL - 103
SP - 2401
EP - 2409
JO - Proceedings of the IEEE
JF - Proceedings of the IEEE
IS - 12
M1 - 7289345
ER -